A 32kb 90nm 10T-cell sub-threshold SRAM with improved read and write SNM

The constraints of power saving have compelled SRAM designers to consider sub-threshold area as a viable choice. The biggest barrier of this progress is the stability of SRAM's cells and the correct operations. In this paper a 10T cell structure has been proposed with 90% read and 50% write SNM improvement in comparison to the conventional 6T cell. The hold SNM value is about the 6T cell SRAM. Also using differential read method in the proposed structure causes high read performance and using simpler sense amplifier. The symmetric configuration of this structure helps the SRAM has simpler layout and lower transistor mismatch. Using 90nm TSMC CMOS, 32kb 10T cell SRAM in sub-threshold area is simulated that confirms the proposed structure performance.